SI5335D-B01740-GM QFN-24-EP clock generator/frequency synthesizer/PLL SILICON LABS original stock
Si5335 is a highly flexible clock generator capable of synthesizing four completely non integer related frequencies up to 350 MHz. The device has four sets of outputs, each supporting one differential pair or two single ended outputs. Using the patented multi synthesis fractional frequency divider technology from Silicon Lab, all outputs are guaranteed to have a frequency synthesis error of 0 ppm, regardless of configuration, allowing multiple clock integrated circuits and crystal oscillators to be replaced with one device.
Si5335 supports up to three independent, pin selectable device configurations, allowing one device to replace three independent clock generators or buffer integrated circuits. In order to simplify system design, a maximum of 5 user assignable and pin selectable control pins are provided, supporting PCIe compatible spread spectrum control, main and/or individual output enable, frequency plan selection, and device reset.
Two selectable PLL loop bandwidths support jitter attenuation in applications such as PCIe and DSL. Through its flexible clock builder ™ (www.silabs. com/ClockBuilder) Network configuration tool, factory customized, pin controlled equipment within two weeks, with no minimum order quantity limit. Measuring PCIe clock jitter is a fast and easy tool to use with silicon laboratory PCIe clock jitter.
enables independent, any-frequency
synthesis of four frequencies
Configurable as a clock generator or
clock buffer device
Three independent, user-assignable, pinselectable device configurations
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS
Flexible input reference:
External crystal: 25 or 27 MHz
CMOS input: 10 to 200 MHz
SSTL/HSTL input: 10 to 350 MHz
Differential input: 10 to 350 MHz
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS/CML: 1 to 350 MHz
HCSL: 1 to 250 MHz
CMOS: 1 to 200 MHz
SSTL/HSTL: 1 to 350 MHz
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Up to five user-assignable pin
functions simplify system design:
SSENB (spread spectrum control),
RESET, Master OEB or OEB per pin,
and Frequency plan select 1 GbE and 10 GbE Functional Block Diagram
(FS1, FS0)
Loss of signal alarm
PCIe Gen 1/2/3/4 common clock
compliant
PCIe Gen 3 SRNS Compliant
Two selectable loop bandwidth
settings: 1.6 MHz or 475 kHz
Easy to customize with web-based
utility
Small size: 4 x 4 mm, 24-QFN
Low power (core):
45 mA (PLL mode)
12 mA (Buffer mode)
Wide temperature range: –40 to
+85 °C
