Js28f256p30tfe tsop-56 memory MgO agent spot

General Description

The Micron Parallel NOR Flash memory is the latest generation of Flash memory devi

ces. Benefits include more density in less space, high-speed interface device, and sup

port for code and data storage. Features include high-performance synchronous-burst

read mode, fast asynchronous access times, low power, flexible security options, and

three industry-standard package choices. The product family is manufactured using Mi

cron 65nm process technology.

The NOR Flash device provides high performance at low voltage on a 16-bit data bus.

Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page

mode read. Configuring the read configuration register enables synchronous burst

mode reads. In synchronous burst mode, output data is synchronized with a user-sup

plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technol

ogy that enables fast factory PROGRAM and ERASE operations. Designed for low-volt

age systems, the devIce supports READ operations with VCC at the low voltages, and

ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered en

hanced factory programming (BEFP) provides the fastest Flash array programming per

formance with VPP at VPPH, which increases factory throughput. With VPP at low voltag

es, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to

voltage flexibility, a dedicated VPP connection provides complete data protection when

VPP ≤ VPPLK.

A command user interface is the interface between the system processor and all inter

nal operations of the device. The device automatically executes the algorithms and tim

ings necessary for block erase and program. A status register indicates ERASE or PRO

GRAM completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation.

Each ERASE operation erases one block. The erase suspend feature enables system soft

ware to pause an ERASE cycle to read or program data in another block. Program sus

pend enables system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

The protection register enables unique device identification that can be used to in

crease system security. The individual block lock feature provides zero-latency block

locking and unlocking. The device includes enhanced protection via password access;

this new feature supports write and/or read access protection of user-defined blocks. In

addition, the device also provides the full-device OTP security feature.

Virtual Chip Enable Description

The 512Mb device employs a virtual chip enable feature, which combines two 256Mb

die with a common chip enable, F1-CE# for QUAD+ packages, or CE# for Easy BGA

packages. The maximum address bit is then used to select between the die pair with F1-

CE#/CE# asserted, depending upon the package option used. When F1-CE#/CE# is as

serted and the maximum address bit is LOW, the lower parameter die is selected; when

F1-CE#/CE# is asserted and the maximum address bit is HIGH, the upper parameter die

is selected.

Features
• High performance
– 100ns initial access for Easy BGA
– 110ns initial access for TSOP
– 25ns 16-word asychronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and
17ns clock-to-data output synchronous burst
read mode
– 4-, 8-, 16-, and continuous word options for burst
mode
– Buffered enhanced factory programming (BEFP)
at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.14 MB/s (TYP)
using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Asymmetrically blocked architecture
– Four 32KB parameter blocks: top or bottom configuration
– 128KB main blocks
– Blank check to verify an erased block
• Voltage and power
– VCC (core) voltage: 1.7V to 2.0V
– VCCQ (I/O) voltage: 1.7V to 3.6V
– Standy current: 65µA (TYP) for 256Mb
– 52 MHz continuous synchronous read current:
21mA (TYP), 24mA (MAX)
• Security
– One-time programmable register: 64 OTP bits,
programmed with unique information from Micron; 2112 OTP bits available for customer programming
– Absolute write protection: VPP = VSS
– Power-transition erase/program lockout
– Individual zero-latency block locking
– Individual block lock-down
– Password access
• Software
– 25μs (TYP) program suspend
– 25μs (TYP) erase suspend
– Flash Data Integrator optimized
– Basic command set and extended function Interface (EFI) command set compatible
– Common flash interface
• Density and Packaging
– 56-lead TSOP package (256Mb only)
– 64-ball Easy BGA package (256Mb, 512Mb)
– QUAD+ and SCSP packages (256Mb, 512Mb)
– 16-bit wide data bus
• Quality and reliabilty
– JESD47 compliant
– Operating temperature: –40°C to +85°C
– Minimum 100,000 ERASE cycles per block
– 65nm process technology