Mt41k64m16tw-107it: J fbga-96 storage mgguang agent shipment
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface de
signed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock
cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one
half-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com
mand, and address signals are registered at every positive edge of CK. Input data is reg
istered on the first rising edge of DQS after the WRITE preamble, and output data is ref
erenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad
dress bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row pre
charge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Industrial Temperature
The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when TC exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when TC is < 0°C or
>95°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as
• Complete functionality may be described throughout the document; any page or dia
gram may have been simplified to convey a topic and may not be inclusive of all re
quirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not sup
ported, and can result in unknown operation.
• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,
x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,
x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a
single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
– Connect UDQS to ground via 1kΩ* resistor.
– Connect UDQS# to VDD via 1kΩ* resistor.
– Connect UDM to VDD via 1kΩ* resistor.
– Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float
DQ[15:8].
Features
• VDD = VDDQ = +1.35V (1.283V to 1.45V)
• Backward compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options1
Marking
• Configuration
– 256 Meg x 4
256M4
– 128 Meg x 8
128M8
– 64 Meg x 16
64M16
• FBGA package (Pb-free) – x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev.
G
JP
– 78-ball FBGA (8mm x 10.5mm) Rev. J
DA
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm) Rev. G
JT
– 96-ball FBGA (8mm x 14mm) Rev. J
TW
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
-107
– 1.25ns @ CL = 11 (DDR3-1600)
-125
– 1.5ns @ CL = 9 (DDR3-1333)
-15E
– 1.87ns @ CL = 7 (DDR3-1066)
-187E
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C)
None
– Industrial (–40°C ≤ TC ≤ +95°C)
IT
• Revision
:G / :J