Mt40a256m16ge-083e: B fbga-96 memory mgguang original agent

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config

ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach

ieve high-speed operation. The 8n-prefetch architecture is combined with an interface

designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit

wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit

wide, one-half-clock-cycle data transfers at the I/O pins.

Industrial Temperature

An industrial temperature (IT) device option requires that the case temperature not ex

ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double

when TC exceeds 85°C; this also requires use of the high-temperature self refresh option.

Additionally, ODT resistance and the input/output impedance must be derated when

operating outside of the commercial temperature range, when TC is between –40°C and

0°C.

Features
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V, –125mV/+250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• TC maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write and read leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination
(ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test (x16)
• sPPR and hPPR capability
• JEDEC JESD-79-4 compliant
Options1 Marking
• Configuration
– 1 Gig x 4 1G4
– 512 Meg x 8 512M8
– 256 Meg x 16 256M162
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 11.5mm) – Rev. A HX
– 78-ball (9mm x 10.5mm) – Rev. B RH
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. A HA
– 96-ball (9mm x 14mm) – Rev. B GE
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200) -062E
– 0.682ns @ CL = 20 (DDR4-2933) -068E
– 0.682ns @ CL = 21 (DDR4-2933) -068
– 0.750ns @ CL = 18 (DDR4-2666) -075E
– 0.750ns @ CL = 19 (DDR4-2666) -075
– 0.833ns @ CL = 16 (DDR4-2400) -083E
– 0.833ns @ CL = 17 (DDR4-2400) -083
– 0.937ns @ CL = 15 (DDR4-2133) -093E
– 0.937ns @ CL = 16 (DDR4-2133) -093
– 1.071ns @ CL = 13 (DDR4-1866) -107E
• Operating temperature
– Commercial (0° ื TCื 95°C) None
– Industrial (–40° ื TCื 95°C) IT
– Revision :A
:B