P25q32h-uxh-ir uson8 flash memory chip original stock
2p25q32 is a serial interface flash memory device designed for a variety of consumer based applications, where program code is executed from flash shadow to embedded or external RAM. The device has a flexible erasure architecture, and its page erasure granularity is also an ideal choice for data storage, eliminating the need for additional data storage devices.
The device's erase block size has been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase block, memory space can be * used effectively. Since some code modules and data storage segments must be left in their own erasure area, the memory waste and unused memory space of large segment and large block erasure flash memory devices can be greatly reduced. This improved memory space efficiency allows the addition of additional code routines and data storage segments while still maintaining the same overall device density.
The device also contains an additional 3 * 1024 byte OTP lock security register, which can be used for device serialization, system level electronic serial number (ESN) storage, lock key storage and other purposes.
The device is specifically designed for many different systems and supports read, program, and erase operations with a wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.
1 Overview
Average
single 2.3V to 3.60v power supply
industrial temperature range - 40 ° C to 85 ° C
serial peripheral interface (SPI) compatibility: mode 0 and mode 3
single, double, four SPI, QPI
-Standard SPI: SCLK, CS, Si, so, WP, hold#
-Dual SPI: SCLK, CS, IO0, IO1, WP, hold#
-IV SPI: SCLK, cs#, IO0, IO1, io2, IO3
-QPI:SCLK，CS#，IO0，IO1，IO2，IO3
flexible code and data storage architecture
-Unified 256 byte page program
-Unified 256 byte page erase
-Unified 4K byte sector erase
-Unified 32K / 64K byte block erase
-Full chip erase
hardware control locking of the protected sector through WP pin
one time programmable (OTP) safety register
-3 * 1024 byte security register with OTP lock
128 bit one ID for each device
* * programming and erasing speed
-2ms page program time
-10 ms page erase time
-10ms 4K byte sector erase time
-10ms 32K byte block erase time
-10ms 64K byte block erase time
JEDEC standard manufacturer and equipment ID reading method
* low power consumption
-0.3ua deep power drop current
-10uA standby current
-1.0mA active reading current at 33MHz
-2.5mA activation program or erase current
high reliability
-100000 program / erase cycles
-20 year data retention period
industry standard green packaging options
-8-pin SOP (150mil / 208mil)
-8-land USON（3x2x0.55mm，3x4x0.55mm）-8-land WSON（6x5x0.75mm）
-8-pin tssop
-KGD of SIP
The device's erase block size has been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase block, memory space can be * used effectively. Since some code modules and data storage segments must be left in their own erasure area, the memory waste and unused memory space of large segment and large block erasure flash memory devices can be greatly reduced. This improved memory space efficiency allows the addition of additional code routines and data storage segments while still maintaining the same overall device density.
The device also contains an additional 3 * 1024 byte OTP lock security register, which can be used for device serialization, system level electronic serial number (ESN) storage, lock key storage and other purposes.
The device is specifically designed for many different systems and supports read, program, and erase operations with a wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.
1 Overview
Average
single 2.3V to 3.60v power supply
industrial temperature range - 40 ° C to 85 ° C
serial peripheral interface (SPI) compatibility: mode 0 and mode 3
single, double, four SPI, QPI
-Standard SPI: SCLK, CS, Si, so, WP, hold#
-Dual SPI: SCLK, CS, IO0, IO1, WP, hold#
-IV SPI: SCLK, cs#, IO0, IO1, io2, IO3
-QPI:SCLK，CS#，IO0，IO1，IO2，IO3
flexible code and data storage architecture
-Unified 256 byte page program
-Unified 256 byte page erase
-Unified 4K byte sector erase
-Unified 32K / 64K byte block erase
-Full chip erase
hardware control locking of the protected sector through WP pin
one time programmable (OTP) safety register
-3 * 1024 byte security register with OTP lock
128 bit one ID for each device
* * programming and erasing speed
-2ms page program time
-10 ms page erase time
-10ms 4K byte sector erase time
-10ms 32K byte block erase time
-10ms 64K byte block erase time
JEDEC standard manufacturer and equipment ID reading method
* low power consumption
-0.3ua deep power drop current
-10uA standby current
-1.0mA active reading current at 33MHz
-2.5mA activation program or erase current
high reliability
-100000 program / erase cycles
-20 year data retention period
industry standard green packaging options
-8-pin SOP (150mil / 208mil)
-8-land USON（3x2x0.55mm，3x4x0.55mm）-8-land WSON（6x5x0.75mm）
-8-pin tssop
-KGD of SIP