Xc2c256-6vqg100c vqfp-100 programmable logic device price advantage

describe

Cooling runner ™- The ii256 macro battery device is designed for high-performance and low-power applications. This saves power for high-end communication equipment and high-speed for battery driven equipment. Due to the low-power standby operation and dynamic operation, the overall reliability of the system is improved

The device consists of 16 functional blocks connected by a low-power advanced interconnect matrix (AIM). Aim provides 40 real and supplementary inputs to each function block. The function block consists of a PLA with 40 to 56 P items and 16 macro units, which contain many configuration bits and allow the operation mode of combination or registration.

In addition, these registers can be globally reset or preset and configured as a D or T trigger or as a D latch. There are also multiple clock signals, including global and local product term types, which are configured based on each macro unit. The output pin configuration includes rotation rate limit, bus holding, pull up, open drain and programmable grounding. Schmidt trigger inputs can be based on each input pin. In addition to storing the macrocell output status, the macrocell register can also be configured as a "direct input" register to directly store the signal from the input pin.

The clock can be used on a global or function block basis. Three global clocks can be used for all function blocks as a synchronous clock source. Macro unit registers can be individually configured to support zero or one state. The global set / reset control line can also be used to set or reset selected registers asynchronously during operation. Additional local clock, synchronous clock enable, asynchronous setting / reset and output enable signals can be formed using product terms on a per macrocell or per function block basis.

The dualdedge trigger function can also be used on a per macrocell basis. This feature allows high-performance synchronous operation based on low-frequency clock to help reduce the total power consumption of the device.

The circuit also includes dividing an externally provided global clock (gck2) into 8 different options. This will produce clock frequencies divided by even and odd numbers.

The combined cool clock characteristics are obtained by clock division (divided by 2) and dualdedge trigger.

Datagate is a method of selectively disabling CPLD inputs that are not of interest at some point in time. By mapping the signal to the datagate function, the signal switching can be reduced to achieve lower power.

Another feature that simplifies voltage conversion is I / O banking. There are two I / O units on the coolrunner-ii256 macro battery device, which can easily interface with 3.3V, 2.5V, 1.8V and 1.5V devices.

The I / O of coolrunner-ii256 macro battery CPLD is compatible with various I / O standards (see Table 1). The device is also 1.5vi/o compatible using Schmidt trigger input.

Real digital design technology

Xilinx cooling runner -iicpld is manufactured based on 0.18 micron process technology, which is derived from leading FPGA product development. Coolrunner iicpld adopts real digital technology, which is a design technology that uses CMOS technology in both manufacturing and design methods. The actual digital design technology adopts a cascaded CMOS gate to realize the sum of products, rather than the traditional sensory amplifier method. Due to this technology, Xilinx cooling operator iicpld realizes high-performance and low-power operation.

Supported input and output standards

Kuii256 macrocell has lvcmos, LVTTL, SSTL and hstli / O implementation. See Table 1 for input / output standard voltage. LVTTL input / O standard is a general EIA / JEDEC standard for 3.3V applications using LVTTL input buffer and push-pull output buffer. Lvcmos standard is used for 3.3V, 2.5V and 1.8V applications. Both HSTL and sstli / O standards use VREF pins to meet JEDEC requirements. The input voltage of cpi-5ldo / runner is also compatible with cpi-iio

features

• optimized for 1.8V systems

-Needle specific delay up to 5.7 NS

-As low as 13 μ A quiescent current

• the industry's best 0.18 micron CMOS CPLD

-The architecture is optimized for effective logic synthesis.

Refer to coolrunner ™- 2、 Family data sheet schema description.

-Multi voltage I / O operation - 1.5V to 3.3V

• multiple package options

-100 pin vqfp with 80 user I / O

-144 pin TQFP with 118 user I / O

-132 spherical CP (0.5mm) BGA with 106 user I / O

-208 pin PQFP with 173 user I / O

-256 ball feet (1.0 mm) BGA with 184 user I / O

-All packages are provided with lead-free packaging

• advanced system functions

-Fastest system programming

·IEEE 1532.8v interface used by ISP

-IEEE1149。 1 JTAG boundary scan test

-Optional Schmitt trigger input (per pin)

-Unmatched low power management

·Data gate enable (DGE) signal control

-Two independent I / O groups

-Realdigital 100% CMOS Product terminology generation

-Flexible clock mode

·Optional double edge trigger register

·Clock divider (divided by 2,4,6,8,10,12,14,16)

·Cool clock

-Global signal option with macro unit control

·Multiple global clocks, each with phase selection macro cells

·Multiple global output support

·Global setup / reset

-Advanced design security

-PLA building

·Excellent Pinot retention

·100% product term cross functional routability block

-Open drain output options for wired or LED

drive

-Optional bus hold, three state or weak pull-up

Selected I / O pin

-Optional configurable grounding on unused I / O

-And 1.5V, 1.8V,

2.5V and 3.3V logic levels

·Sstl2-1, sstl3-1 and hstl-1 I / O compatibility

-Hot pluggable