Xc95144xl-5tq100c tqfp-100 programmable logic device price advantage
describe
Xc95144xl is a 3.3vcpld control system, which can be used in high-performance and low-voltage applications in cutting-edge communication and computing systems. It consists of eight 54v18 function blocks, provides 3200 available gates, and the propagation delay is 5ns.
Power estimation
The power consumption of CPLD can vary greatly according to the system frequency, design application and output load. To help reduce power consumption, each macrocell in the xc9500xl device can be configured in low-power mode (starting from the default high-performance mode). In addition, unused product terms and macro units are automatically deactivated by the software to further save power. For the general estimation of ICC, the following formula can be used:
ICC(mA)=MCHS(0.175*PTHS+0.345)+MCLP(0.052*PTLP+0.272)+0.04*MCTOG(MCHS+MCLP)*f
Where: mchs = # high-speed cells in high-speed configuration PTHs = average number of high-speed product terms MCLP = # macro cells in low-power configuration PTLP = average low-power product terms f = maximum clock frequency mctog = average% switching per clock (~ 12%)
This calculation comes from laboratory measurements of xc9500xl components populated with 16 bit counters and allows a single output (LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation.
features
• 5 ns for pin logic delay
• system frequency up to 178 MHz
• 144 macro units, 3200 available gates
• small size packaging
-100 pin TQFP (81 user I / O pins)
-144 pin TQFP (117 user I / O pins)
-144-csp (117 user I / O pins)
-All packages are provided with lead-free packaging
• optimized for high performance 3.3V systems
-Low power operation
-The 5V tolerance I / O pin can accept 5V, 3.3V and 2.5V signals
-3.3V or 2.5V output capacity
-Advanced 0.35 micron feature size CMOS
flash ™ technology
• advanced system functions
-Programmable in system
-Excellent pin locking and wiring capabilities
Quick connect ™ II switch matrix
-Ultra wide 54 input function block
-Up to 90 product terms per macro unit
Individual product term assignment
-Three global and one local clock reverses
Product terminology clock
-Separate output enable for each output pin with local
reversal
-Input hysteresis on all user and boundary scan pins
input
-Bus hold circuit on all user pin inputs
-Full IEEE standard 1149.1 boundary scan (JTAG)
• fast parallel programming
• conversion rate control for a single output
• enhanced data security
• excellent quality and reliability
-Durability over 10000 programming / erasing
cycle
-20 year data retention period
-ESD protection over 2000V
• pin compatible with 5V core xc95144 device
100 pin TQFP package
Warning: programmed temperature range
TA = 0 ° C to + 70 ° C
Xc95144xl is a 3.3vcpld control system, which can be used in high-performance and low-voltage applications in cutting-edge communication and computing systems. It consists of eight 54v18 function blocks, provides 3200 available gates, and the propagation delay is 5ns.
Power estimation
The power consumption of CPLD can vary greatly according to the system frequency, design application and output load. To help reduce power consumption, each macrocell in the xc9500xl device can be configured in low-power mode (starting from the default high-performance mode). In addition, unused product terms and macro units are automatically deactivated by the software to further save power. For the general estimation of ICC, the following formula can be used:
ICC(mA)=MCHS(0.175*PTHS+0.345)+MCLP(0.052*PTLP+0.272)+0.04*MCTOG(MCHS+MCLP)*f
Where: mchs = # high-speed cells in high-speed configuration PTHs = average number of high-speed product terms MCLP = # macro cells in low-power configuration PTLP = average low-power product terms f = maximum clock frequency mctog = average% switching per clock (~ 12%)
This calculation comes from laboratory measurements of xc9500xl components populated with 16 bit counters and allows a single output (LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation.
features
• 5 ns for pin logic delay
• system frequency up to 178 MHz
• 144 macro units, 3200 available gates
• small size packaging
-100 pin TQFP (81 user I / O pins)
-144 pin TQFP (117 user I / O pins)
-144-csp (117 user I / O pins)
-All packages are provided with lead-free packaging
• optimized for high performance 3.3V systems
-Low power operation
-The 5V tolerance I / O pin can accept 5V, 3.3V and 2.5V signals
-3.3V or 2.5V output capacity
-Advanced 0.35 micron feature size CMOS
flash ™ technology
• advanced system functions
-Programmable in system
-Excellent pin locking and wiring capabilities
Quick connect ™ II switch matrix
-Ultra wide 54 input function block
-Up to 90 product terms per macro unit
Individual product term assignment
-Three global and one local clock reverses
Product terminology clock
-Separate output enable for each output pin with local
reversal
-Input hysteresis on all user and boundary scan pins
input
-Bus hold circuit on all user pin inputs
-Full IEEE standard 1149.1 boundary scan (JTAG)
• fast parallel programming
• conversion rate control for a single output
• enhanced data security
• excellent quality and reliability
-Durability over 10000 programming / erasing
cycle
-20 year data retention period
-ESD protection over 2000V
• pin compatible with 5V core xc95144 device
100 pin TQFP package
Warning: programmed temperature range
TA = 0 ° C to + 70 ° C